1. Field of the Invention
The present invention relates to a method for forming a metallization layer of a semiconductor device.
2. Background of the Related Art
In a metal oxide semiconductor (MOS) device, metallization layers can be used to form or to interconnect a gate electrode, source and drain impurity diffused regions, a contact region, and each device with one another. Characteristics of an electrode metallization layer depend on the device feature dimensions, and the power source voltage. The resistance of a gate electrode increases as the number of features on a given chip increase. Capacitance also increases as metallization layer pitch is reduced. This, in turn, decreases signal transmission speed, thereby reducing an operation speed of the device.
Since resistance of a contact region can increase as much as K.sup.2, where K is the number of individual devices on a chip, and since current density can increase by a factor of K, reliability of a metallization layer deteriorates as K increases. In addition, the reliability of a metallization layer can deteriorate due to electromigration (EM) effects. For these reasons, a material of low resistance is typically used to form a gate electrode, which can serve as a word line of a memory. The resistivity of doped polysilicon is typically greater than 200 .mu..OMEGA..multidot.cm. If polysilicon is used as a material of a gate electrode, when the device dimensions are less than 1 .mu.m, operation speed is reduced due to a delay in signal transmission, thereby deteriorating reliability of the semiconductor device.
To reduce resistance, a tungsten silicide WSi.sub.x film may be used to form a gate electrode. The tungsten silicide WSi.sub.x film has excellent step coverage, and its resistivity is about 100 .mu..OMEGA..multidot.cm. Also, a WSi.sub.x film may be easily deposited on polysilicon. In other words, polycide (polysilicon+refractory silicide) may be used as a gate electrode. However, it is known that a WSi.sub.x film having a resistivity of about 100 .mu..OMEGA..multidot.cm fails to sufficiently reduce resistance if the dimensions of a gate electrode are less than about 0.5 .mu.m. To solve the resistivity problem, the use of other metallization layer materials such as W (resistivity of 10 .mu..OMEGA..multidot.cm or less), TiSi.sub.2 (resistivity of 20 .mu..OMEGA..multidot.cm or less), COSi.sub.2 (resistivity of 20 .mu..OMEGA..multidot.cm or less), and TiN (resistivity of 30 .mu..OMEGA..multidot.cm or less) have been studied.
Further, as the packing density of a semiconductor device increases, an aspect ratio of a contact hole for electrical connection of devices increases. The increased aspect ratio has also caused problems with step coverage.
A background art method for forming a metallization layer of a semiconductor device will be described with reference to FIGS. 1A to 1C, which are sectional views illustrating process steps of forming a metallization layer of a semiconductor device. As shown in FIG. 1A, an oxide film 2 is first deposited on a semiconductor substrate 1, and a photoresist PR is deposited on the oxide film 2. A region where a contact hole will be formed is then defined, and the photoresist PR in the region is selectively patterned by exposure and developing processes. Subsequently, the oxide film 2 is selectively removed, by an etching process using the patterned photoresist PR as a mask, so that a contact hole 3 is formed to expose the semiconductor substrate 1. At this time, the oxide film 2 forms an interlayer dielectric layer (ILD).
As shown in FIG. 1B, the photoresist PR is removed. A barrier metal layer 4 of Titanium(Ti)/Titanium Nitride (TiN) is then formed on the semiconductor substrate 1 in the contact hole 3 and on an entire surface of the oxide film 2. The barrier metal layer 4 is to prevent characteristics of a metallization layer, which will be formed later, from being varied.
For contact holes having a high aspect ratio, an overhang can occur at predetermined portions on sides A of the contact hole 3, or at a corner portion B of the bottom of the contact hole 3. In other words, the barrier metal layer 4 may not be fully deposited at the comer portion B of the bottom of the contact hole 3. Such an overhang frequently occurs when forming contact holes of a memory device with a capacity of 64M or more. Thus, the oxide film 2 is often exposed at the comer portion B of the bottom of the contact hole 3.
To prevent such an overhang from occurring, a collimator may be used to fully deposit the barrier metal layer 4 on the bottom corners of the contact hole 3. Alternatively, a deposition time may be extended to ensure the barrier metal layer 4 is deposited on the corner portion B of the bottom of the contact hole 3.
As shown in FIG. 1C, a tungsten layer 5 is then formed on an entire upper surface of the barrier metal layer 4, by a chemical vapor deposition (CVD) method. In the CVD method, a chemical material, which includes atoms of a material to be deposited, is provided to a reaction chamber. The chemical material (in a gas state) is reacted with another gas in the reaction chamber to generate a desired material. The desired material is then deposited on a surface of the substrate, and unnecessary materials (including gas) are exhausted from the reaction chamber.
The process steps of forming the tungsten layer 5 will be described in detail. First, a seed layer (not shown) of amorphous silicon is formed on the barrier metal layer 4 by flowing SiH.sub.4 gas on the entire surface of the substrate. The reaction path is SiH.sub.4 (gas).fwdarw.amorphous Si+2H.sub.2 (gas). During this step, SiH.sub.4 gas flows for about five seconds at 25 Standard Cubic Centimeter per Minute (SCCM).
Subsequently, both SiH.sub.4 gas and WF.sub.6 gas flow on the barrier metal layer 4, and a first portion of the tungsten layer 5 is deposited. The reaction path is 3SiH.sub.4 (gas)+2WF.sub.6 (gas).fwdarw.2W+3SiF.sub.4 +6H.sub.2 (gas). The tungsten layer 5 has property of 2 W. The tungsten (2 W) has a relatively fast deposition ratio and excellent adhesion.
A second portion of the tungsten layer 5 is then deposited on the first portion of tungsten at a slower deposition rate. In this step, H.sub.2 gas and WF.sub.6 gas flow on the first portion of the tungsten layer 5, and the second portion of the tungsten layer 5 is deposited by the reaction path 3H.sub.2 (gas)+WF.sub.6 (gas).fwdarw.W+6HF (gas). The second portion of the tungsten layer is deposited at a slower deposition rate to achieve better step coverage.
The background art method for forming a metallization layer of a semiconductor device has several problems. Because the barrier metal layer 4 has an overhang, when the tungsten layer 5 is deposited on the barrier metal layer 4, a void 6 may be formed in the tungsten layer 5.
Also, WF.sub.6 gas may come into contact with TiN of the barrier metal layer in the contact hole during the course of the chemical reaction that occurs when depositing the tungsten layer. The WF.sub.6 gas may react with Ti, thereby generating TiF.sub.3 gas. The TiF.sub.3 gas may cause sparking to occur, which may cause an electrical short between adjacent metallization layers if an interval between the metallization layers is small. In addition, because the substrate may remain exposed at bottom comers of the contact hole 3, WF.sub.6 gas may directly diffuse into the semiconductor substrate. As a result, leakage current may occur, and characteristics of the device are deteriorated.
A collimator may be used to reduce the overhang effect, or a deposition time of the barrier metal layer may be increased to ensure the barrier metal layer is formed across an entire bottom surface of the contact hole 3. However, if the collimator is used, the formation process time increases. Also, if the deposition time of the barrier metal layer is increased to ensure the barrier metal layer covers the bottom comers of the contact hole, the overhang problem may become worse.
If the barrier metal layer is not formed at the comer portions of the bottom of the contact hole, WF.sub.6 gas may be distributed into the interface between Ti (in the barrier metal layer) and the oxide film in the contact hole during the chemical reaction for deposition of the tungsten layer. Fluorine (F) of the WF.sub.6 gas causes poor adhesion of the interface between the oxide film and the Ti, thereby deteriorating reliability in metallization of the semiconductor device.